In high speed Ethernet controllers, such as gigabit Ethernet controllers, data is transferred at relatively high rates. In one instantiation, the driver/receiver circuitry for facilitating receipt of data from a network and transmission of data to a network for interface to the media side of the controller is contained within a Physical Layer Device (PHY) which is operable to interface with the Media Independent Interface (MII) side through a Media Access Controller (MAC) block. One side of the PHY connects to the physical media (transmission media), while the other side connects to the Media Independent Interface (MII)/Gigabit Media Independent Interface (GMII). Data is received by the PHY from the transmission medium and then transmitted to the MAC for a receive operation. During a transmit operation, data is transferred from the MAC to the PHY and the PHY then transmits the data onto the transmission medium. Each of the MAC and PHY have independent clocks such that a data clock is always transmitted with the data (except for the 10/100 mode). Due to the high data rate in the gigabit controller, some timing compensation is required between chips to ensure that the clock and data are properly aligned at the receiving one of the PHY and MAC blocks. The reason for this is that the clock edge of the data clock in the transmitter is utilized to generate data and then is also utilized at the opposite end, the receive end, to sample the data (for the RGMII mode). To ensure that the sampling is done only during “data valid” windows, there is provided some delay at the transmit end to ensure that data is sampled correctly. One method of doing this is to provide a fixed delay for the data to ensure that the data is positioned relative to the rising edge of the receive clock to ensure that the “data valid” region is disposed within the period of the receive clock at the appropriate position for the purpose of sampling of the data. This requires that there be a separate delay for each data line between the PHY and the MAC at the PHY on the receive path associated therewith. For a typical Gigabit Media Independent Interface (GMII), there are provided ten interface lines for transmitting receive data along the receive path, eight for the actual receive data and two for the receive data error and data valid signals. In another type of interface, a Ten Bit Interface (TBI), there are provided ten bits of data transfer. The number of pins associated with the GMII interface can be reduced with a Reduced GMII (RGMII) interface that requires only five data bits to transfer data and control information. However, there will always be a receive clock transmitted from the PHY to the MAC for received data along with the data for any of the interfaces, such that reconstruction thereof at the MAC by sampling will require some delay to be incorporated, since the data is clocked from the rising edge of the receive clock, due to some timing issues. Further, for accurate sampling of all of the data, this delay must be tightly controlled.